Intel reaches 'tentative settlement' with FTC
The FTC have been gunning for Intel of late (and you could argue quite rightly so) - As a result, it seems as though a settlement has now been reached between the chip-making giant and said regulatory body.
The legalese in the settlement terms (PDF) is a little tough to wade through, but from my understanding, a few things stand out:
The Tech Report helpfully outlines the key points of the settlement.- Intel has to include a standard PCI Express interface in its high-volume platforms for the next six years. The chipmaker isn't allowed to "design any Required Interface to intentionally limit the performance or operation of any Relevant GPU in a manner that would render the Required Interface non-compliant with the applicable PCIe Base Specification."
- Intel isn't allowed to make any design changes to its products if those changes degrade the performance of competing products without positively impacting its own products. If such a change were to occur because of a bug, Intel would have to demonstrate that it was indeed inadvertent.
- Within 90 days of the order becoming effective, Intel has to "Clearly and Prominently" inform customers who purchased its compilers whether those compilers "optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors." In addition, Intel has to reimburse customers who have "detrimentally relied on Intel representations as to compiler availability, functionality, or effectiveness."
- Intel has to confirm that Via is allowed to make and sell x86 microprocessors, and as far as I can tell, Intel also has to extend Via's patent licensing agreement until 2018.
- Intel can't offer or deny benefits to customers or end users based on their use of competing products, and it must retain "all written contracts" pertaining to the purchase and sale of relevant products for five years.
- If one of its competitors changes ownership, Intel has to wait 30 days before initiating patent litigation, and it has to enter into "good faith negotiations regarding the future patent relationship" with that competitor.
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PCI Express 3.0: On motherboards by this time next year?
PCI Express 3.0 is coming, and may well appear on motherboards a year from now - Should it be something that you get excited about?
The primary difference for end users between PCI Express 2.0 and PCI Express 3.0 will be a marked increase in potential maximum throughput. PCI Express 2.0 employs 5 GT/s signaling, enabling a bandwidth capacity of 500 MB/s for each “lane†of data traffic. Thus, a PCI Express 2.0 primary graphics slot, which typically uses 16 lanes, offers bidirectional bandwidth of up to 8 GB/s.
PCI Express 3.0 will double those numbers. PCI Express 3.0 uses an 8 GT/s bit rate, enabling a bandwidth capacity of 1 GB/s per lane. Accordingly, a 16-lane graphics card slot will have a bandwidth capacity of up to 16 GB/s.
On the surface, the increase from 5 GT/s to 8 GT/s doesn’t quite sound like a doubling of speed. However, PCI Express 2.0 uses an 8b/10b encoding scheme, where 8 bits of data are mapped to 10-bit symbols to achieve DC balance. The result is 20% overhead, cutting effective bit rate.
PCI Express 3.0 moves to a much more efficient 128b/130b encoding scheme, eliminating the 20% overhead. So, the 8 GT/s won’t be a “theoretical†speed; it will be the actual bit rate, comparable in performance to 10 GT/s signaling with 8b/10b.
Tom's Hardware have more about what to expect from PCI Express 3.0 and when.PCI Express 3.0 will double those numbers. PCI Express 3.0 uses an 8 GT/s bit rate, enabling a bandwidth capacity of 1 GB/s per lane. Accordingly, a 16-lane graphics card slot will have a bandwidth capacity of up to 16 GB/s.
On the surface, the increase from 5 GT/s to 8 GT/s doesn’t quite sound like a doubling of speed. However, PCI Express 2.0 uses an 8b/10b encoding scheme, where 8 bits of data are mapped to 10-bit symbols to achieve DC balance. The result is 20% overhead, cutting effective bit rate.
PCI Express 3.0 moves to a much more efficient 128b/130b encoding scheme, eliminating the 20% overhead. So, the 8 GT/s won’t be a “theoretical†speed; it will be the actual bit rate, comparable in performance to 10 GT/s signaling with 8b/10b.
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